As semiconductor technology continuously advances, layout-dependent effects (LDEs) have become crucial issues in analog circuit design. Characteristics like threshold voltage and mobility of devices are sensitive to LDEs. Moreover, an imperfect layout structure affects performance in unexpected ways. As such, layout-generation in recent analog circuit design is challenged by LDEs. Regarding LDE optimization, a layout-generating method is needed to automatically and efficiently consider these LDEs as constraints during the partitioning and floorplanning stages.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.